Resource Planning within Top SLR - Resource Planning within Top SLR - 2026.1 English - UG1387

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)

Document ID
UG1387
Release Date
2026-07-22
Version
2026.1 English

The following figure shows the Versal HBM HBM stacked silicon interconnect device. Unlike UltraScale+ HBM devices, this device places the HBM stacks at the top of the device in yellow.

The green highlights indicate the HNoC and the red highlights indicate the VNoC. Consider floorplanning modules that are directly connected to the HBM interface in the top SLR, adjacent to HBM stacks. This avoids SLR crossing and improve routability and timing closure.

Also, perform a capacity check for the modules in the top SLR with Pblock statistics. If you have many HBM interfaces routing over the next SLRs, then the long line routing demands are high in the top adjacent SLR. This cannot have enough routing resources for the local logic in the SLR. Therefore, anticipate this and try to reduce the local logic to avoid any routing congestion.

Figure 1. Resource Planning in Versal HBM Stacked Silicon Interconnect Device