In this example, the pipeline registers use a mix of synchronous and asynchronous resets. This mix is present in the logic that targets the dedicated DSP resources. This mix causes suboptimal mapping of the multiplier-accumulator to the DSP primitives.
The following figure shows a 16x16-bit DSP58-based multiplier using input pipeline registers with asynchronous reset and multiplier output registers with synchronous reset. Synthesis must use regular fabric registers for the input stages. The DSP output (DSP58 M and P registers) packs the multiplier register with synchronous reset. This adds up to 32 extra fabric registers, and the DSP58 results in the configuration: AREG/BREG=0, MREG=1, PREG=1.
You can rewrite the preceding example to use a single type of reset for all pipeline registers. This change takes advantage of existing DSP primitive features. It involves changing the mix of asynchronous reset and synchronous reset on pipeline registers.
The following figure shows how to change the reset definition in the RTL. This change ensures all pipeline registers around the multiplier logic use a single reset type. The reset type can be either synchronous or asynchronous. By making this change, synthesis can take advantage of the DSP58 internal registers (AREG/BREG=1, MREG=1, PREG=1).