Report Timing from or to the Port - Report Timing from or to the Port - 2026.1 English - UG1387

You can use the report_timing command to identify the related clocks in the design. This applies whether the port is already constrained or not. Define all the timing clocks first.

Then, report the worst path from or to the I/O port. Create the I/O delay constraint relative to the reported clock. Finally, rerun the same timing report from/to the other clocks of the design.

If the port seems related to more than one clock, create the corresponding constraint, then repeat the process. For example, the clocks clk1 and clk2 inside the design relate to the din input port:

report_timing -from [get_ports din] -sort_by group

The report shows that the din port is related to clk1. The input delay constraint is (for both min and max delay in this example):

set_input_delay -clock clk1 5 [get_ports din]

Rerun timing analysis using the same command as before. Observe that din is also related to clk2 because the -sort_by group option reports N paths per endpoint clock. You can add the corresponding delay constraint. Then, rerun the report to validate that the din port is not related to another clock.

You can also run the same analysis using the Timing Summary report with the -report_unconstrained option. With only clock constraints in your design, the Unconstrained Paths section appears as follows:

------------------------------------------------
| Unconstrained Path Table
------------------------------------------------
Path Group   From Clock   To Clock   
----------   ----------   --------   
(none)
(none)     clk1
(none)     clk2
(none)             clk1
(none)             clk2

Fields without a clock name (or <NONE> in the Vivado IDE) refer to a group of paths. The startpoints (From Clock) or endpoints (To Clock) of these paths do not associate with a clock. The unconstrained I/O ports fall in this category. You can retrieve their name by browsing the rest of the report.

For example in the Vivado IDE, select the Setup paths for the clk1 to NONE category. You can see the ports driven by clk1 in the To column:

After adding the new constraints and applying them in memory, you must rerun the report to determine which ports are still unconstrained. For most designs, increase the number of reported paths to ensure the report lists all I/O paths.