Register replication can increase the speed of critical paths by making copies of registers to reduce the fanout of a given signal. This gives the implementation tools more flexibility in placing and routing the different loads and associated logic. Synthesis tools use this technique extensively.
Most synthesis tools use a fanout threshold limit to automatically determine whether to duplicate a register. Lowering this global threshold allows automatic duplication of high fanout nets. You cannot control the duplication of registers or the grouping of their loads.
In addition, the global replication mechanism does not assess timing slack accurately. This inaccuracy can lead to unnecessary replicated cells. It can also lead to an increase in logic utilization. It can potentially lead to higher power consumption.
For high frequency designs, a better approach to reducing fanout is to use a balanced tree for the high fanout signals. Consider manually replicating registers based on the design hierarchy, because the cells included in a hierarchy are often placed together.
The following figure shows the balanced reset tree. The high fanout reset flip-flop (FF) RST2 is replicated in RTL. This replication balances the fanout across the different modules. If required, physical synthesis can perform further replication to improve WNS based on placement information.
Do not replicate registers used for synchronizing signals that cross clock domains. The presence of the ASYNC_REG attribute on these registers prevents the tool from replicating these registers. If the synchronizing chain has a high fanout and replication must meet timing, add an extra register after the synchronization chain. Do not apply the ASYNC_REG constraint to this extra register.