A clock enable signal controls the source and destination sequential cells, activating the clock every N cycles. The following example has a clock enable active every three cycles, with the same clock for both startpoint and endpoint:
Figure 1. Enabled Flops with Same Clock Signal
Figure 2. Timing Diagram for Setup/Hold Check
Constraints:
set_multicycle_path -from [get_pins REGA/C] -to [get_pins REGB/D] -setup 3
set_multicycle_path -from [get_pins REGA/C] -to [get_pins REGB/D] -hold 2Figure 3. Setup/Hold Checks Modified After Multicycle Specification
Note: With the first command, as the setup capture
edge moved to the third edge. This movement was by two cycles from its default position.
At the same time, the hold edge also moved by two cycles. The second command is for
bringing the hold edge back to its original location by moving it again by two cycles
(in the reverse direction).
Refer to this link in the Vivado Design Suite User Guide: Using Constraints (UG903) for more information on common multicycle path scenarios. These scenarios include phase shift and multicycle paths between synchronous clocks.
Important: The clock phase shift does
not modify the clock waveform. The clock modifying block includes it in the insertion
delay. You do not need to add a setup-only multicycle path. This ensures proper timing
of the path from or to the clock. For more information, refer to this link in the
Vivado
Design Suite User Guide: Design Analysis and Closure
Techniques (UG906).