Following are the main design topologies for Versal devices:
- RTL as top
- BD as top
All Versal designs include a block diagram for some portion of the design. You must configure the CIPS/PS Wizard and the NoC IP using a block design (BD). RTL as top and BD as top describe how the block design fits into the larger design.
The design generates the block diagram portion in an RTL-as-top design. It stitches this portion as a submodule into the rest of the RTL hierarchy. The design does not limit itself to a single BD in the RTL hierarchy.
For example, the CIPS/PS Wizard and the NoC can reside on one BD and transceivers can be on a second BD. These designs can be compiled independently and can both be stitched as a submodule into the rest of the RTL hierarchy. This provides you with some flexibility in how you partition your design.
In a BD as top design, the block diagram stitches together all of the design sources. You can package these sources and add them to the block design as IP. Alternatively, you can reference them using RTL module referencing. You can incorporate additional block designs into the top-level design using block design containers (BDCs).
The most significant impact the design topology has on the overall project is the interaction between the hardware and software. When using a BD as top design topology, the hardware hand-off file seamlessly passes all information about software and hardware interaction. RTL does not yet provide a similar level of transparency. Following are recommendations for when to use each design topology:
- Choose RTL as top if you can manually create the device tree and install drivers for the design peripherals.
- Choose BD as top if you want a seamless hardware hand-off.