Recommendations for Designing with Versal Device IP - Recommendations for Designing with Versal Device IP - 2026.1 English - UG1387

Versal devices include unique IP that require special consideration as follows:

• Include the Control, Interface, and Processing System (CIPS) or Processing System (PS Wizard) IP in your design.

  The CIPS/PS Wizard IP must be present in every Versal adaptive SoC design. This IP contains the platform management controller (PMC) required to boot and configure the device. If your design does not include CIPS/PS Wizard IP, a post-link/pre-place DRC flags your design.

  For descriptions of the PMC and PS, refer to the following documents:

  • Versal Adaptive SoC Technical Reference Manual (AM011)
  • Versal AI Edge Series Gen 2 and Prime Series Gen 2 Technical Reference Manual (AM026)

  For more information on CIPS IP or PS Wizard IP, refer to the following documents:

  • Control, Interface and Processing System LogiCORE IP Product Guide (PG352)
  • Processing System Wizard LogiCORE IP Product Guide (PG450)

  For more information on the CPM, excluding the VP1902, refer to the following documents:

  • Versal Adaptive SoC CPM CCIX Architecture Manual (AM016)
  • Versal Adaptive SoC CPM Mode for PCI Express Product Guide (PG346)
  • Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)
• Configure the CPM controller, including GT selection, through the CIPS/PS Wizard IP (excluding the VP1902).

  For information, refer to the Versal Adaptive SoC CPM Mode for PCI Express Product Guide (PG346). The PL access to the PCIe® interface can be configured using the PCI Express® IP through the IP catalog. For more information on PCIe, refer to the following documents:

  • Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)
  • Versal Adaptive SoC PCIe PHY LogiCORE IP Product Guide (PG345)
  • Versal Adaptive SoC CPM Mode for PCI Express Product Guide (PG346)
  • Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)
• Conduct upfront analysis and early validation of NoC resource design requirements.

  The NoC IP acts as a logical representation of the physical NoC. The Vivado IP integrator aggregates the connectivity and quality of service (QoS) information to form a unified traffic specification. For more information on the NoC and integrated memory controller IP and performance tuning, refer to the following documents:

  • Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)
  • Programmable Network on Chip (NoC2) LogiCORE IP Product Guide (PG406)
  • Integrated DDR5/LPDDR5/5X Memory Controller LogiCORE IP Product Guide (PG456)
• Use the Advanced I/O Planner to assign the DDR memory controller physical locations and pins. For more information, refer to the Advanced IO Wizard LogiCORE IP Product Guide (PG320).

  The NoC IP integrates the hardened DDR memory controllers. The NoC compiler selects a location for the DDR memory controller while aggregating design requirements. During implementation, the NoC IP appropriately adjusts the physical assignments of the DDR memory controllers.

• Use SmartConnect only for connections that require AXI4-Lite. Use it to supplement the NoC when the rest of the design fully consumes the NoC bandwidth. Also, use it when there are not enough NoC ports.

  The NoC is the preferred method for moving data throughout the Versal device. For more information, refer to the SmartConnect LogiCORE IP Product Guide (PG247).

• Configure the Versal adaptive SoC transceivers using the Versal adaptive SoC Transceivers Wizard Subsystem IP.

  Use the Hard Block Planner to assign the physical locations of the GT quads in Versal adaptive SoC designs. For information on the Hard Block Planner, refer to the  Vivado Design Suite User Guide: I/O and Clock Planning (UG899). For information on the full GT quad layout and supported configuration options, refer to the  Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002) and Versal Adaptive SoC GTM Transceivers Architecture Manual (AM017).

• Use the three methods to configure the Versal adaptive SoC Transceiver Wizard Subsystem IP. The Versal adaptive SoC Transceiver Wizard Subsystem IP is documented in the Versal Adaptive SoC Transceiver Subsystem Product Guide (PG442).
• For the traditional Versal adaptive SoC Transceiver Wizard IP, use block automation in the IP integrator to assist with connections between IP and the GTs. For an overview of creating a design with GT parent IP, refer to this link in the Versal Adaptive SoC Transceivers Wizard LogiCORE IP Product Guide (PG331).
• Use the Bridge IP to connect custom IP to the Versal adaptive SoC GT quads.

  For more information, refer to this link in the Versal Adaptive SoC Transceivers Wizard LogiCORE IP Product Guide (PG331).