You can add a module or entity definition from a Verilog, VHDL, or a BD RTL wrapper source file directly into your block design. This approach provides a way to quickly adding RTL modules. It does not require packaging the RTL as an IP to add it through the Vivado IP catalog.
The system infers any generics or parameters contained in the source RTL when you add the module to the block design. You can also configure them in the Re-customize Module Reference dialog box for a selected module. You must insert attributes into the HDL code so that interfaces, clocks, resets, interrupts, addresses, and clock enables are correctly inferred. For BD module references, the BD wrapper automatically creates these attributes and the BD module reference consumes them at creation.
In addition, there is no parameter propagation across boundaries. You must use the attributes to support DRCs run by IP integrator when validating the design. For example, IP integrator provides DRCs for validating the clock frequency between the source clock and the destination. By specifying the correct frequency in the RTL code, you can ensure that your design connectivity is correct.
Following is important information to note when using RTL module references:
- The Module Reference feature in the IP integrator allows inferencing of the XCI (.xci extension) files for IP embedded within the RTL code. Although most IP are supported for inferencing, a few are not. For more information, including a list of unsupported IP, refer to this link in the Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994).
- The RTL module definition cannot include netlists, such as EDIF or DCP. It also cannot include another module set as out-of-context (OOC) inside the RTL module.
- VHDL and Verilog are the only supported languages for module definition. The module or entity definition at the top-level of the RTL module does not support SystemVerilog and VHDL 2008.
- You cannot package a block design that contains a module reference as an IP. Instead, you must package the module as an IP separately, and then package the BD including that IP.
The following figure shows the design hierarchy for a BD. This BD contains two RTL module references. One reference contains RTL and the other contains another BD.