There are multiple ways of breaking a memory configuration to serve a particular requirement. The requirement for a particular design can be clock frequency, power, or a mixture of both.
The following example highlights the different structures that can be generated to achieve your requirements. Synthesis can limit the cascading of the block RAM for the clock frequency/power trade-off using the CASCADE_HEIGHT attribute. The usage and arguments for the attribute are described in the Vivado Design Suite User Guide: Synthesis (UG901).
The following figure shows an example of 4Kx32 memory configuration for achieving a higher clock frequency (timing).
This implementation always enables all block RAMs (for each read or write), so they consume more power.
The following figure shows an example of cascading all the block RAMs for low power.
In this implementation, the system selects one block RAM at a time from each unit. This selection reduces the dynamic power contribution to almost half. Block RAMs have a dedicated cascade MUX and routing structure. This structure allows the construction of wide, deep memories that require more than one block RAM primitive. You can build these memories in a power efficient configuration.
The following figure shows an example of how to limit the cascading. It also shows how to gain both power and clock frequency at the same time. You often achieve this without sacrificing performance.
This implementation selects two block RAMs at a time. The dynamic power contribution is better than for the high clock frequency structure. It is not as good as for the low power structure. The advantage of this structure compared to a low power structure is that it uses only two block RAMs in the cascaded path. This has impact on the target frequency when compared to four block RAMs in the critical path for the low power structure.