Define generated clocks in the transitive fanout of their master clock, unlike primary clocks. This allows the timing engine to accurately compute their insertion delay. Failure to follow this rule results in improper timing analysis and most likely in invalid slack computation.
The following figure shows that the system uses gen_clk_reg/Q as a clock for the next flop (q_reg). It is also in the fanout cone of the primary clock c1. Hence gen_clk_reg/Q
must have a create_generated_clock on it, rather than a
create_clock.
Figure 1. Generated Clock in the Fanout Of Master Clock
create_generated_clock -name GC1 -source [get_pins gen_clk_reg/C] -divide_by 2
[get_pins gen_clk_reg/Q]