Parallel Clock Buffers - Parallel Clock Buffers - 2026.1 English - UG1387

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)
Document ID
UG1387
Release Date
2026-07-22
Version
2026.1 English

Use parallel clock buffers to achieve the following results:

  • Ensure predictable placement across implementation runs.

    The same input clock port, MMCM, XPLL, DPLL, or GT*_QUAD directly drives the parallel clock buffers. The system alwasys places the buffers in the same clock region as their driver. This placement occurs regardless of netlist changes or logic placement variation.

  • Match the insertion delays between parallel branches of the clock tree.

    AMD recommends parallel buffers over cascaded clock buffers, especially when there are synchronous paths between the branches. The clock insertion delay does not match between the branches of the clock trees when you use cascaded buffers. This remains true even when using the CLOCK_DELAY_GROUP or USER_CLOCK_ROOT constraints. This can result in high clock skew, which makes timing closure challenging if not impossible.

Note: If possible, use the MBUFG* cells to minimize skew on synchronous CDC timing paths. Alternatively, use the MBUFG* cells when matching the insertion delay of multiple related clock networks. When using the MBUFG* cells, you must not use the CLOCK_DELAY_GROUP constraint.

The following figure shows three parallel global clock buffers driven by the MMCM CLKOUT0 port.

Figure 1. Parallel BUFGCE on MMCM Output