In the out-of-context (OOC) synthesis flow, the system synthesizes certain levels of hierarchy separately from the top-level. Synthesize the out-of-context hierarchy first. Then, the top-level synthesis is run, and each of the out-of-context runs are treated as a black box. AMD IP cores often run in out-of-context synthesis mode.
After all of the out-of-context synthesis runs and top-level synthesis runs are complete, you open the top-level synthesized design. When you do, the Vivado tools assemble the design from all of the synthesis runs. This flow offers the following advantages:
- Reduces compile time for subsequent synthesis runs. You resynthesize only the runs you specify, leaving the other runs unchanged.
- Ensures stability when design changes occur. The system resynthesizes only the runs that include changes.
The disadvantage of this flow is that it requires additional setup. You must be careful in selecting which modules to set as out-of-context synthesis modules. Define any additional XDC constraints separately. Use them only for the out-of-context synthesis runs.
The following figure shows a design that has a top-level synthesis run (synth_1) and two lower-level out-of-context synthesis runs.
For more information on setting up out-of-context synthesis runs, refer to this link in the Vivado Design Suite User Guide: Synthesis (UG901).