Optimal CLOCK_ROOT Placement - Optimal CLOCK_ROOT Placement - 2026.1 English - UG1387

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)

Document ID
UG1387
Release Date
2026-07-22
Version
2026.1 English
Important: AMD recommends creating a Pblock for complete control of your placement and USER_CLOCK_ROOT selection. This Pblock must contain all loads of your clock network. Then, assign the USER_CLOCK_ROOT to a clock region that contains the vertical clock spine. In most cases, the Vivado placer selects the optimal CLOCK_ROOT for your design, and the manual USER_CLOCK_ROOT assignment is not necessary.

The USER_CLOCK_ROOT assignment can be a suboptimal solution in some cases. It does not center upon all loads and creates an unbalanced clock tree. In this case, the placer ignores the USER_CLOCK_ROOT constraint and assigns an optimal CLOCK_ROOT to the clock net.

For example, the system sets the USER_CLOCK_ROOT to X3Y2, but places the loads in X3Y3. In both clock regions, the vertical clock spine exists. However, the optimal solution is to use clock region X3Y3 for the CLOCK_ROOT. The placer issues a message to indicate the optimal solution.

A CLOCK_ROOT can be suboptimal because it does not optimize for a specific critical path or area. An example of this is SLR crossing. If you consider a clock tree to be two flops, the clock tree branches and route independently to each flop. SLR crossings benefit from having the shortest clock tree length after the branching point. Optimize CLOCK_ROOT by moving the Y root coordinate closer to the SLR crossing and the X coordinate toward faster SLR crossings.