SSI technology requires special attention during NoC planning. Familiarize yourself with the SSI technology requirements and recommendations.
To optimize performance when designing with SSI technology devices, partition the design using floorplanning techniques. Target specific SLRs. Keep the utilization of each SLR within guidelines. Attempt to reduce the number of critical signals crossing SLR boundaries. This also involves proper planning of the I/O interfaces, clocks, and logic associated with the floorplan.
The NoC compiler does not consider location constraints when run within the Vivado IP integrator. After the post-synthesis is open in memory, you can floorplan the NoC interface locations to optimal SLR and refresh the NoC solution in the Vivado IDE. Increasing the distance between NMU to NSU can challenge latency. Designers must assess and address this challenge early in the design cycle.
To optimize power when designing with SSI technology devices, reduce SLR crossings and constrain routes to stay in one VNoC column.
Assigning logic to Pblocks with Versal adaptive SoC SSI technology devices can require NoC design planning. This ensures optimal and consistent results throughout your design process. When performing NoC design planning, consider the following guidelines:
- When using SLR-level Pblocks in the implementation tools, consider constraining the NoC NMU/NSU in the Vivado IP integrator to match the implementation results.
- For NoC paths beginning or ending at DDR memory controller or PS, consider placing these paths in SLR0 to minimize latency.
- For NoC paths not beginning or ending at DDR memory controller or PS, consider completely constraining these paths within SLRs (other than SLR0).
- Instead of pipelining across multiple SLRs using the AXI register slice, consider using the NoC.
In the following example, the PL-NoC paths highlighted in purple interface with the DDR memory controller. The IP integrator constrains them to SLR0. The IP integrator constrains the PL-NoC paths, highlighted in pink, to SLR1.