The Vivado IP integrator invokes the NoC Compiler during block design validation to generate a NoC placement and routing solution to meet QoS requirements. If the IP integrator solution does not meet design implementation requirements, you can invoke the NoC Compiler during design placement. This action generates a new solution to meet the implementation requirements.
Figure 1. NoC Compiler Flow
Following are implementation requirements that can cause the NoC Compiler to be invoked during design placement:
- Physical location or Pblock constraints applied to the PL that influences NoC NMU/NSU placement
- Resolution of the NoC interface between CIPS/PS Wizard and NoC for proper assignment to the targeted device
- Top-level port assignment of DDR memory controller interfaces that results in a change in DDR memory controller assignment
- Global placement of programmable logic that influences NoC NMU/NSU placement
Tip: In the IP integrator, you
can constrain the location of the DDR memory controller. Constrain it to the appropriate
site in the NoC View. This setting reflects the assignment to perform during design
placement. This improves the NoC QoS results correlation between IP integrator and a
fully implemented design.