After synthesizing the design, assign I/Os and clock logic constraints as recommended by AMD. For Versal devices, AMD recommends instantiating all IP and I/Os along with basic logic in an RTL project. You can then synthesize the project.
For designs using GT blocks, such as MRMAC or DCMAC, the Hard Block Planner provides a visual help. It helps assign the GT Quad and the GT reference clock to valid sites and package pins.
AMD IP includes memory interfaces and high-speed I/O interfaces. The Advanced IO Wizard/X5IO Wizard allows correct-by-construction pinout assignment for AMD IP.
For legacy, low-performance interfaces using I/O logic, you can perform pinout by drag-and-drop onto the Package window.