Multi-Clock Buffer (MBUFG) - Multi-Clock Buffer (MBUFG) - 2026.1 English - UG1387

MBUFGs are clocking primitives. They allow you to use the leaf-level clock dividers. These dividers are driven by the local horizontal clock distribution tracks in Versal devices. The leaf-level division uses only one global clock routing resource. This results in less clock track resource utilization. It also improves power efficiency and skew between synchronous clock domains.

The MBUFG primitives (MBUFGCE, MBUFGCE_DIV, MBUFG_GT, MBUFGCTRL and MBUFG_PS) have four outputs (O1, O2, O3, O4). These outputs configure a clock divider setting of 1, 2, 4, and 8 for any leaf clock divider driving connected clock loads. MBUFG primitives can help to reduce the high skew between synchronous clock domains. For more information, refer to this link in the Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388).

Select the MBUFG primitives when running the Versal adaptive SoC Clocking Wizard. This allows you to use MBUFG primitives instead of standard BUFG primitives in your design. The MBUFG primitives are only available when the output frequencies are multiple to each other by a factor of 2, 4, or 8. For more information, refer to this link in the Clocking Wizard for Versal Adaptive SoC LogiCORE IP Product Guide (PG321).

The following figure shows logical and physical implementation views of a MBUFG-driven clocking network. The Vivado router configures the BUFDIV_LEAF primitives, which are route-through primitives. The logical netlist does not represent these primitives. You can use the CLRB_LEAF input on the MBUFG primitives to asynchronously reset the BUFDIV_LEAF dividers. The system automatically routes a signal from the MBUFG CLRB_LEAF pin to the connected BUFDIV_LEAF CLR_B pin.

The global clock routing and distribution tracks route the 1x clock. As a result, MBUFG-driven clocks preserve clocking resources. The common node for paths clocked by two output clocks of the same MBUFG is typically much closer to the driver and the load. This proximity reduces clock skew and eases timing closure.

Figure 1. MBUFGCE Logical and Physical View

On device startup, the BUFDIV_LEAF clock dividers are reset, and the MBUFG output clocks start up in the High state. In the following cases, special handling is required. This handling ensures that the BUFDIV_LEAF dividers are reset to their startup state before the MBUFG receives an input clock or is enabled again.

• If you reset the MBUFG clock buffer or a clock modifying block that drives an MBUFG during device operation.
• If the clock driving the MBUFG violates the minimum pulse width specification after device startup, the clock modifying block is not locked.
• If the MBUFG-driven clock network is part of a reconfigurable partition

Assert the CLRB_LEAF pin of the MBUFG Low to reset the BUFDIV_LEAF buffers. The user logic must stop the MBUFG clock before the CLRB_LEAF pin is asserted Low. Hold the clock inactive for a predetermined amount of time after the CLRB_LEAF signal is deasserted High. This ensures proper device operation.

After you deassert the CLRB_LEAF signal, you must hold the clock inactive longer than the maximum pin delay time. The router reports the maximum pin delay time for routing the signal connected to the MBUFG CLRB_LEAF pin to the BUFDIV_LEAF CLR_B pins. The router reports this time in an INFO message as shown in the following example. A 10 ns delay is sufficient in most cases to satisfy the CLRB_LEAF net route delay.

INFO: [Route 35-3345] MBUFG*/CLRB_LEAF net route delay summary. Please
ensure that the wait time between de-asserting the CLRB_LEAF signal to 
each MBUFG and enabling the MBUFG output clocks is greater than the 
delay listed in the table below.
+------------------+-------------+--------------------+--------------------+
| MBUFG Cell       | Site        | CLRB_LEAF Net Name | Max Pin Delay (ns) |
+------------------+-------------+--------------------+--------------------+
| U_engine/bufg_fx | BUFGCE_X3Y0 | U_engine/p_1_out   | 2.252              |
+------------------+-------------+--------------------+--------------------+

The Clocking Wizard IP automatically adds a circuit to meet this reset requirement. For more information, refer to the Clocking Wizard for Versal Adaptive SoC LogiCORE IP Product Guide (PG321).

The following figure shows the timing relationship required between asserting the MBUFGCE_DIV CLRB_LEAF and CE signals after asserting CLR. Hold the CE signal Low to stop the clock. Wait until the CLRB_LEAF signal propagates to all BUFDIV_LEAF CLR_B pins. In this example, set the CE_TYPE property of the MBUFGCE_DIV to SYNC.

Figure 2. Timing Relationship Between Asserting CLRB_LEAF and CE Signals When CLR is Asserted on an MBUFGCE_DIV

You can use the Clock Utilization Report in the Vivado IDE to visually analyze clocking resource utilization and clock routing. The following figure shows the clock resource utilization per clock region overlaid in the Device window. For more information on this report, refer to the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906).

Figure 3. Clock Utilization Report

For more information on the BUFGCE, MBUFGCE, BUFGCE_DIV, BUFGCTRL, and MBUFGCTRL buffers, refer to the Versal Adaptive SoC Clocking Resources Architecture Manual (AM003). For details on connectivity and use of the BUFG_GT and MBUFG_GT buffers, refer to the following documents:

• Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)
• Versal Adaptive SoC GTM Transceivers Architecture Manual (AM017)