Memory and Advanced I/O Interfaces - Memory and Advanced I/O Interfaces - 2026.1 English - UG1387

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)
Document ID
UG1387
Release Date
2026-07-22
Version
2026.1 English

When using AMD Memory IP, Advanced IO Wizard IP, and X5IO Wizard IP, you must perform additional I/O pin planning steps. After you customize the IP, assign the top-level IP ports to physical package pins in the elaborated or synthesized design in the Vivado IDE. The system groups all ports associated with each Memory IP, Advanced IO Wizard IP, or X5IO Wizard IP into an I/O Port Interface. This grouping allows for easier identification and assignment.

The Advanced I/O Planner assists you in assigning I/O pin groups to XPHY NIBBLESLICEs on the XPIO physical device pins. It also helps with assigning them to CMPHY_OCTADs and XCVR_2Xs on the X5IO physical device pins.

For more information, refer to the following documents or the appropriate product guide for your memory IP:

  • This link in the Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010)
  • This link in the Advanced IO Wizard LogiCORE IP Product Guide (PG320)
  • This link in the X5IO Wizard LogiCORE IP Product Guide (PG455)
Important: For information on design and pinout guidelines, refer to this link in the Versal Adaptive SoC PCB Design User Guide (UG863). Follow the trace length match recommendations in this guide. Verify the correct termination. Validate the pinout by running the DRCs after I/O assignment in the Advanced I/O Planner.
Note: The X5IO also supports MIPI CPHY and DPHY. For information on pinouts, refer to this link in the Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010) and this link in the MIPI RX C-PHY/D-PHY LogiCORE IP Product Guide (PG435).