The following figure shows early stages in the design flow. These stages include C, C++, and RTL synthesis. They have a much higher impact on design performance, density, and power than later implementation stages. If the design does not meet timing, latency, or power goals, AMD recommends revisiting the synthesis stages. This includes C, C++, HDL, and constraints, rather than iterating for a solution in the implementation stages only.
Figure 1. Impact of Design Changes Throughout the Flow
