Mapping Memories to UltraRAM Blocks - Mapping Memories to UltraRAM Blocks - 2026.1 English - UG1387

UltraRAM is a larger memory block with two ports using a single clock. The UltraRAM is included in addition to block RAM resources. Configure the UltraRAM as 4Kx72, 8Kx36, 16Kx18, or 32Kx9.

Use one of the following methods to incorporate UltraRAM into your design:

• Rely on synthesis to infer UltraRAMs by setting the ram_style = "ultra" attribute on a memory declaration in HDL.
• Instantiate AMD XPM_MEMORY primitives.
• Instantiate UltraRAM UNISIM primitives.

The following code example shows the instantiation of XPM memory and is available in the HDL Language templates. Highlighted parameters MEMORY_PRIMITIVE and READ_LATENCY are the key parameters to infer memory as UltraRAM for optimal resource mapping efficiency.

• MEMORY_PRIMITIVE = "ultra" specifies the memory is to be inferred as UltraRAM.
• READ_LATENCY defines the number of pipeline registers present on the output of the memory.

An UltraRAM matrix maps larger memories. It consists of multiple UltraRAM cells configured as row x column structures.

Create a matrix with single or multiple columns based on the depth. The default UltraRAM column height threshold is 8. You can control it using the CASCADE_HEIGHT attribute.

The difference between single column and multiple column UltraRAM matrix is as follows:

• Single column UltraRAM matrix uses the built-in hardware cascade without fabric logic.
• Multiple column UltraRAM matrix uses built-in hardware cascade within each column, plus some fabric logic for connecting the columns. Extra pipelining can be required to maintain achievable clock frequency. Increasing the read latency controls this. The Vivado tools automatically pack these registers into UltraRAM as required.
  Figure 1. Specifying UltraRAM in RTL Code (via XPM)
  
  

The preceding example uses a 32 K x 72 memory configuration, which uses eight UltraRAMs. To increase the maximum clock frequency of the UltraRAM, more pipelining registers must be added to the cascade chain. Increase the read latency parameter value to achieve this.

For more information on inferring UltraRAM in Vivado synthesis, refer to this link in the Vivado Design Suite User Guide: Synthesis (UG901).