The MBUFG primitive in Versal devices allows clock division at the leaf level to reduce clock track utilization and improve timing closure on synchronous CDCs. For DFX designs, MBUFG optimization is allowed only for static clock nets, internal RM clock nets, or usage of only the undivided O1 output at the RP boundary.
Vivado now supports divided outputs (O2, O3, O4) of MBUFGCE primitives as boundary clock nets, subject to the requirements in this section.
Supported Usage
The following configuration is supported:
- The MBUFGCE instance is in the Static region.
- One or more divided outputs (O2, O3, O4) drive loads within a single RM.
Required Design Methodology
- O1 Boundary Clock Connection
- You must connect the O1 output of the MBUFGCE to the RM through a hierarchical boundary pin.
- The O1 output defines the routed boundary clock net. Vivado implements divided clocks (O2/O3/O4) using BUFDIV_LEAF resources near the loads. Vivado derives PPLOC assignment and clock region expansion from the O1 boundary clock net.