Your code finally has to map onto the resources present on the device. Make an effort to understand the key arithmetic, storage, and logic elements in the architecture you are targeting. Then, as you code the functionality of the design, anticipate the hardware resources to which the code maps. Understanding this mapping gives you an early insight into any potential problem.
The following examples demonstrate how understanding the hardware resources and mapping can help make certain design decisions:
- Use a carry chain for addition, subtraction, and
add-sub larger than eight bits. One LUT per 2-bit addition is used. An 8-bit by
8-bit adder uses 8 LUTs and the associated carry chain.
Ternary addition uses two LUTs per 3-bit addition. When the result of an adder is added to another value without a register, two LUTs per 3-bit addition are used. An 8-bit by 8-bit by 8-bit addition uses 16 LUTs and the associated carry chain.
- In general, DSP blocks target multiplication.
Signed bit widths of 27x24 or less and unsigned widths of 26x23 or less map into a
single DSP Block. Multiplication requiring larger products can map into more than
one DSP block. DSP blocks have pipelining resources inside them.
Pipelining properly for logic inferred into the DSP block can greatly improve maximum clock frequency and reduce power. When a multiplication is described, three levels of pipelining around it generates best setup, clock-to-out, and power characteristics. Extremely light pipelining, with one-level or none, can lead to timing issues and increased power for those blocks. Meanwhile, the pipelining registers within the DSP lie unused.
- A single LUT can map two SRLs with depths of 16 bits or less. It can also map single SRLs up to 32 bits.
- For conditional code resulting in standard MUX
components:
- A single LUT can implement a 4-to-1 MUX, yielding in one logic level.
- Three LUTs can implement an 8-to-1 MUX, yielding two logic (LUT) levels.
- Five LUTs can implement a 16-to-1 MUX, yielding effectively two logic (LUT) levels.
For general logic, take into account the number of unique inputs for a given register. From that number, an estimation of LUTs and logic levels can be achieved. In general, six inputs or fewer always results in a single logic level. Theoretically, two levels of logic can manage up to 36 inputs.
For all practical purposes, you must assume that approximately 20 inputs is the maximum that two levels of logic can manage. In general, requiring more inputs and a more complex logic equation increases the number of LUTs and logic levels needed.