Issues When Trying to Eliminate Reset in HDL Code - Issues When Trying to Eliminate Reset in HDL Code - 2026.1 English - UG1387

When optimizing the code to eliminate reset, commenting out the conditions within the reset declaration does not create the required structures and instead creates issues. For example, the following figure shows three pipeline stages with asynchronous reset used for each. If you comment out the code with the reset condition, you attempt to eliminate the reset condition for two pipeline stages. This action enables the asynchronous reset, which is the inverted logic of rst.

Figure 1. Commenting Out Code with Reset Conditions

The optimal way to remove the resets is to create separate sequential logic procedures. Create one procedure for reset conditions and another for non-reset conditions, as shown in the following figure.

Figure 2. Separate Procedural Statements for Registers With and Without Reset