Create small connectivity designs to validate each interface on the device. These small designs exercise only the specific hardware interface, which enables the following:
- Full DRC checks on pinout, clocking, and timing
- Hardware test design after board return
- Rapid implementation in the Vivado tools for faster interface debug
There are multiple options to assist in generating test data for these interfaces. For some of the interface IP cores, the Vivado tools can provide the test designs:
- IBERT for SerDes
- Example design within IP cores
You need to create a separate design for a system-level test in a production environment. Usually, this is a single design that includes tested interfaces and optionally includes processors. You can construct this design using the small connectivity designs to take advantage of design reuse. Although you do not need this design early in the flow, it enables better DRC checks and early software development. You can quickly create it with the Vivado IP integrator.