The most low-level and direct method of controlling clocking structures is to instantiate the required clocking resources into the HDL design. This allows you to access all possible capabilities of the device and exercise absolute control over them. When using BUFGCE, BUFGMUX, BUFGCE_DIV, or other clocking structure that requires extra logic and control, instantiation is generally the only option. However, even for simple buffers, sometimes the quickest way to obtain a required result is to be direct and instantiate it into your design.
An effective style to manage clocking resources is to contain them in a separate entity or module. This is especially important when instantiating. Instantiate the separate entity or module at the top or near the top of the code. Place it at the top-level of code to easily distribute it to multiple modules in your design.
Be aware of where clocking resources can and need to be shared. Creating redundant clocking resources wastes resources. It generally consume more power, creates more potential conflicts, and placement decisions. This results in longer overall implementation tool compile times and potentially leads to more complex timing situations. This is another reason why having the clocking resources near the top module is important.