When you create a block design, the system saves BD file (.bd extension) to the project source file. The Vivado tools cannot directly synthesize IP integrator BD sources. There are two ways to instantiate a BD file:
- BD top
The top-level RTL file instantiates the BD file. The top-level RTL is a wrapper that can be automatically generated and contains only a single instance of the BD. AMD recommends this approach for Versal adaptive SoC designs. However, you do not have to use it.
This approach ensures that the hardware handoff to the system software occurs seamlessly and uses the recommended Versal adaptive SoC design structure. The software identifies all addressable components in the design. It ensures the proper creation of the device tree and drivers.
- RTL top
The top-level RTL file instantiates the BD file, custom logic, and IP. In some cases, you can also instantiate one or more BD files in sub-levels of the hierarchy.
This approach allows the most flexibility for traditional designs migrating to Versal adaptive SoC. The RTL top approach supports successful hardware handoff only if certain conditions are met. A single BD must contain the complete addressing scope. The BD must be instantiated in the hierarchy below the top-level RTL file. In any other scenario, the designer is responsible for creating the device tree and loading the necessary software drivers.
The following sections focus on how to incorporate design sources into a block diagram.