Inserting the clocking elements towards the top level allows for easier clock sharing between modules. This sharing can result in fewer clocking resources needed, which helps in resource utilization, improved maximum clock frequency, and power.
Except for the module that creates the clocks, clock paths must only drive down into modules. Any paths that go through (down from top and then back to top) can create a delta cycle problem in VHDL simulation. This issue is difficult and time consuming to debug.