Vivado synthesis automatically specifies a global buffer (BUFG) for all clock structures. This occurs without user intervention. The specification is up to the maximum allowed in an architecture. This applies unless otherwise specified or controlled by the synthesis tool.
As discussed above, the BUFG provides a well-controlled, low-skew network suitable for most clocking needs. You do not need anything additional unless your design clocking exceeds the number or capabilities of BUFGs in the target device.
Applying additional control to the clocking structure can improve jitter characteristics. It can also enhance skew, placement, power, maximum clock frequency, or other characteristics.