You can use incremental synthesis to reuse existing synthesis results. This approach reduces typical synthesis compile times by 50%. When used with the incremental implementation flow, this approach also improves overall compile time and timing closure consistency.
During synthesis, the tool breaks the design into RTL partitions. Incremental synthesis reuses RTL partitions from a previous synthesis run. RTL partitions are typically created along logical hierarchies. Incremental synthesis only runs if the design is large enough that synthesis creates at least four RTL partitions, each containing at least 50000 instances. Instances include both logical hierarchy and RTL primitives.
Following are the different modes available when using the synth_design -incremental_mode <value> command:
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off - The system does not run incremental synthesis.
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quick - Fastest results but no cross boundary optimizations. This mode limits logic operating frequency.
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default - Most logic optimizations enabled, including cross-boundary optimization. Non-incremental synthesis significantly reduces compile time.
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aggressive - This mode enables all optimizations. Non-incremental synthesis significantly reduces compile time.
AMD typically recommends the quick mode only for low-performance designs. Without cross boundary
optimizations, typical designs have reduced clock frequency. If you construct a design
well with registered hierarchical boundaries, it cannot affect the achievable clock
frequency.
RTL changes in a given area cause resynthesis only in that area due to the limits on cross-boundary optimization. Changes in another synthesis partition do not trigger changes beyond that partition. This leads to more reuse and a faster synthesis result.
For other modes, this is not the case, and RTL changes can trigger the resynthesis of more partitions beyond the partition the cell is in. Modify more than 50% of the partitions to trigger a full resynthesis.
For high-performance designs, AMD recommends the default, aggressive, and
off modes. The aggressive and off modes enable more
optimizations. These modes can lead to more resynthesis but higher QoR.
To more aggressively address compile time concerns, you can compare the incremental synthesis against OOC synthesis. IP typically uses OOC synthesis, and the setup is automatic. Global synthesis with incremental synthesis offers the advantage of cross-boundary optimizations as well as compile time benefits. Following are areas to consider:
- Compile time
OOC synthesis is faster because it reduces the amount of code that the tool elaborates each time. The tool elaborates the RTL only if modifications occur within the OOC module.
- Performance
Incremental synthesis has a maximum clock frequency advantage over OOC synthesis, because this mode allows optimizations across OOC boundaries.
- Setup
When you create an OOC synthesis run for non-IP flows, you must create a wrapper if higher modules pass generics/parameters. In addition, you must create a separate timing constraint file to target the OOC-level ports. Incremental synthesis does not have these requirements.
For more information, refer to the Vivado Design Suite User Guide: Synthesis (UG901).