A high fanout clock spans almost all clock regions of a Versal device. It spans almost an entire SLR of a Versal adaptive SoC stacked silicon interconnect (SSI) technology device. The following figure shows a high fanout clock. It spans almost an entire SLR of a Versal adaptive SoC SSI technology device. The XPIO bank BUFGCE driver appears in red.
The clock net occupies a vertical routing resource in both SLR0 and SLR1 but only fans out onto the distribution resource in SLR1. Using more than 24 high fanout clocks in a design can cause issues that require upfront planning. Such planning can include using Pblocks for logical hierarchies within SLRs. Alternatively, it can include assigning LOC constraints to clock sources in the XPIO banks.