Global Synthesis - Global Synthesis - 2026.1 English - UG1387

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)

Document ID
UG1387
Release Date
2026-07-22
Version
2026.1 English

The global synthesis flow synthesizes the full design in one run. This approach offers the following advantages:

  • Allows the synthesis tool to perform the maximum optimization. Because the synthesis tool is aware of the full design, the tool can optimize between hierarchies that other flows cannot.
  • Enables easy analysis after the synthesis run.

The disadvantage of this flow is longer compile time. Every time synthesis is run, the full design is rerun. Use incremental synthesis to mitigate this disadvantage.

Note: If your design includes XDC constraints, you must reference the objects to the top-level design.