Global Constraints Between Clocks in Both Directions - Global Constraints Between Clocks in Both Directions - 2026.1 English - UG1387

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)

Document ID
UG1387
Release Date
2026-07-22
Version
2026.1 English

Use the clock groups when you do not need to limit the maximum latency. Following is an example to ignore paths between clkA and clkB:

set_clock_groups -asynchronous -group clkA -group clkB

Two master clocks and their respective generated clocks can form two asynchronous domains. The system properly synchronizes all paths between these domains. The constraint for clock groups can apply to several clocks simultaneously:

set_clock_groups -asynchronous \
-group {clkA clkA_gen0 clkA_gen1 …} \
-group {clkB clkB_gen0 clkB_gen1 …}

Or simply:

set_clock_groups -asynchronous \
-group [get_clocks -include_generated_clock clkA] \
-group [get_clocks -include_generated_clock clkB]