Gigabit transceivers (GTs) have specific pinout requirements, and you must consider the following:
- Sharing of reference clocks
- Sharing of PLLs within a quad
- Placement of GT hard blocks, such as PCIe or MRMAC, and their proximity to transceivers
Note: Refer to this link in the
Versal Adaptive SoC CPM DMA and Bridge Mode for PCI
Express Product Guide (PG347). This guide shows guidance on
GT selection and pin planning for CPM5.
AMD recommends that you use the GT wizard to generate the core. Alternatively, you can use the AMD IP core for the protocol. You must perform additional I/O pin planning steps when you use AMD transceiver IP.
After you customize the IP, assign the top-level transceiver I/O and REFCLK ports to physical package pins. Do this in either the elaborated or synthesized design using the Hard Block Planner or Pin Planner in the Vivado IDE. For pinout recommendations, refer to the Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347).
Note: For clock resource
balancing, the Vivado placer attempts to constrain
loads clocked by GT output clocks next to the GTs sourcing the clocks.