You can shut down larger portions of the clock network for periods of time. You can enable or disable the clock network using a BUFGCE or BUFGCTRL.
You can slow the clock during certain periods of operation. You can use buffers with additional logic to periodically enable the clock net. Alternatively, you can use a BUFGMUX or BUFGCTRL to switch the clock source from a faster clock signal to a slower clock.
Any of these techniques can effectively reduce dynamic power. However, depending on the requirements and clock topology, one technique can prove more effective than another.
Important: Do not gate a global clock buffer in the MMCME5 feedback path when targeting Versal devices. This path is between the CLKFBOUT and
CLKFBIN pins. Do not use the MMCME5 LOCKED signal for gating. This results in the MMCME5
failing to achieve lock.