A common technique gates the clock or data paths. This stops transitions when these paths' results are not used. Gating a clock stops all driven synchronous loads and prevents data path signal switching and glitches from continuing to propagate.
Power optimization (power_opt_design) can automatically generate signal gating logic to reduce switching activity. However, you have information about the application, data flow, and dependencies that is not available to the tool, which only you can specify.