Each GT interface uses several clocks. Some clocks are shared across bonded GT*_QUAD cells located in one or several GT quads. The Versal device contains GT quads in the left and rightmost clock regions.
Each of the clock regions includes two GT quads, 24 BUFG_GT/MBUFG_GT clock buffers, and one DPLL. Most GT clocks have a low fanout with loads placed locally in the clock region next to the associated GT*_QUAD. Some GT clocks drive loads across the entire device and require the utilization of clock routing resource in many clock regions.