Optimal floorplanning is critical to ensuring timing closure and avoiding routability issues in DFX designs. Rules related to I/O banks in DFX floorplanning can also influence board pinout planning. Following are key areas to consider in floorplanning a DFX design:
- Pblocks
Allocate the maximum amount of resources to the RP Pblock when floorplanning for DFX partitions. Keep minimal resources in the static region to meet the platform compilation requirement.
The guidelines permit but discourage irregular-shaped partition (T or L shapes) because placement and routing in these regions can become challenging.
Multiple RPs can share the same clock region by splitting it horizontally into upper and lower halves. This does not apply to the half clock regions at the top of the PL in some Versal devices.
Multiple RPs share the VNoC tiles. However, if more than two RPs compete to find the clock routing solution in a single VNoC column, it can cause an unroutable situation. If there are more than two RPs, try to keep a clock region gap between them. Do this so that internal clocks of all RPs do ot compete for the solution in the same VNoC tile.
Programmable unit (PU) granularity is typically the tile itself, except for I/Os where granularity is a full I/O bank. This fine granularity allows greater flexibility in floorplanning. For more information on the PU, refer to this link in the Vivado Design Suite User Guide: Dynamic Function eXchange (UG909).
To avoid bleed over of static nets to the RP, you can create a Pblock for that static region with contain routing enabled. However, this approach requires additional considerations with regard to routability of the static logic. For details, refer to the Vivado Design Suite User Guide: Dynamic Function eXchange (UG909).
In Versal devices, avoid disjoint Pblock whenever possible. The Vivado tools determine when two portions of a Pblock are disjoint. They use the corresponding expanded routing footprint for a collection of resources. They mark the portions disjoint if there is a gap between it and another routing footprint section for the same Pblock.
If you cannot use contiguous Pblock, you must create a guided floorplan for disjoint Pblock. Use only clock routing between disjoint sections. For more information on disjoint Pblock, refer to the Vivado Design Suite User Guide: Dynamic Function eXchange (UG909).
- I/Os
Declaring one static I/O in an I/O bank forces all I/O sites in that I/O bank into the static region. However, you can still reconfigure clocking resources.
Previous devices bundled I/O and clocking resources in the same PU. This bundling meant all I/O and clocking resources were either all static or all reconfigured. They cannot reside in separate domains.
- Clocking
If an RP uses a remote clocking tile and needs to cross over another RP, the clock track usage is limited. Its split between the RPs determines the limitation. Use the DPLL in the GT clock region. This region can be local to RP. Do not use MMCM of the horizontal clock region at the bottom of the device.
For more information on clock region, refer to this link in the Vivado Design Suite User Guide: Dynamic Function eXchange (UG909).
- Partition pins
In a DFX design, the reconfigurable module (RM) and static region call signals between them boundary signals. All RM pins must have a partition pin location (PPLOC) deposited on the boundary signal by the placer. The only exceptions are dedicated paths between hard primitives. The partition pin is the physical interface on the PL that separates the static and reconfigurable portions of a boundary signal. For more information on PPLOCs, refer to this link in the Vivado Design Suite User Guide: Dynamic Function eXchange (UG909).
Partition pins reduce the solution space for the router. The router must always route the corresponding boundary net through the partition pin. To alleviate this issue, the DFX flow includes expanded routing. Expanded routing is the additional routing footprint for an RP that can include routing tiles from the static region. For more information on expanded routing, refer to this link in the Vivado Design Suite User Guide: Dynamic Function eXchange (UG909).
You can also reduce the local density of partition pins to avoid routing challenges when implementing future reconfigurable module variants. There are multiple properties like HD.PARTPIN_RANGE and HD.PARTPIN_LOCS to control the placement of partition pins.
For more information on Pblock guidelines, I/O planning, clocking, and PPLOC reduction, refer to the Vivado Design Suite User Guide: Dynamic Function eXchange (UG909).