The following example does not apply to all designs. However, it demonstrates what can be achieved with hierarchy. DSP designs generally let designers add latency to the design. You can add registers to implement a design with a higher clock frequency.
Registers increase placement flexibility. This is important because at high clock frequency, signals cannot traverse the die in one clock cycle. Adding registers can allow hard-to-reach areas to be used. The following figure shows how effective hierarchy planning results in faster timing closure.
There are three levels of hierarchy in this part of the design:
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DSP_iIn the DSP_i algorithm block, both the inputs and outputs are registered. Because registers are plentiful in a device, it is preferable to use this method to improve the timing budget.
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floorplanning_wrapper_iIn
floorplanning_wrapper_i, there is a CE signal. CE signals are typically heavily-loaded and can present a timing challenge. Include them in a floorplan. You can manually floorplan this module later by creating a floorplanning wrapper if needed.In addition, the design adds KEEP_HIERARCHY at the module level. This preserves the hierarchy for floorplanning, regardless of any other global synthesis options.
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placement_flexibility_wrapper_iIn
placement_flexibility_wrapper_i, the DATA_IN, VALID_IN, DATA_OUT and VALID_OUT signals are registered. Because these signals are not intended to be part of the floorplan, they are outsidefloorplanning_wrapper_i. If they were in the floorplan, they cannot fulfill the requirement for placement flexibility.In addition, more registers can be added later as long as both DATA_IN + VALID_IN or DATA_OUT and VALID_OUT are treated as pairs. If more registers are added, the synthesis tool can infer shift register LUTs (SRLs). This forces all registers into one component. It does not help placement flexibility. To prevent this, the design added SHREG_EXTRACT at the module level and set it to NO.