Develop a hardware design using Vivado Project Flows and Vitis tools. Refer to this link in the Embedded Design Development Using Vitis (UG1701). You develop the base hardware design or extensible platform in Vivado. It typically consists of a block design that includes:
- Processing system (PS)
- Network-on-chip (NoC)
- Memory controllers
- Clock sources
- Application-specific IP and RTL modules
The platform also contains a minimally configured AI Engine IP instance with NoC paths needed to configure the array at boot and runtime. The block design annotates potential platform attachment points for Vitis using typed PFM properties. These properties include:
- Control bus
- Memory
- Streaming input/output
- Clocks
Vitis tools compile ADF graphs and kernels into the AI Engine. They compile PL kernels through HLS and link them into the base platform. The tools configure the AI Engine IP, NoC, and other IPs with the platform block design.
You can often develop the AI Engine and PL kernel network against an AMD-provided development platform. You can then integrate them into a custom base platform. The integration uses PFM attachment attributes or makes straightforward changes to a connectivity specification.
AMD provides development platforms to support rapid development of AI Engine and PL kernel networks or subsystems using Vitis tools. They provide integrated hardware and embedded Linux software platforms. These platforms enable you to develop, debug, and analyze subsystems on a board. You can migrate these subsystems into a custom platform.
You can employ similar platform-based design methodology with custom platforms. Adopting a similar integrated hardware/software custom platform is not a requirement for subsystem development. AMD recommends using standard platforms with custom platforms to loosen the coupling between base platform and subsystem design iterations.