A commonly used pipelining technique is to identify a large combinatorial logic path. Break the large path into smaller paths. Introduce a register stage between these smaller paths. Ideally, balance each pipeline stage.
To determine whether a design requires pipelining, identify the frequency of the clocks and the amount of logic distributed across each of the clock groups. You can use the report_design_analysis Tcl command with the -logic_level_distribution option to determine the logic-level distribution for each of the clock groups.
Tip: The design analysis report highlights
the number of paths with zero logic levels. You can use this information to determine
where to modify in your code.