Design Planning for Key IP Blocks - Design Planning for Key IP Blocks - 2026.1 English - UG1387

Versal adaptive SoC includes several essential hard IP. As part of carefully planning your design, you must analyze and configure these IP appropriately for your design.

CIPS IP

The CIPS IP contains several key components for the Versal architecture, including the platform management controller (PMC), the processor subsystems (PS), and the Cache Coherent Interconnect for Accelerators (CCIX) PCIe® Module (CPM). The PMC manages programming and booting the Versal device, monitors the system, and protects the device from harmful attacks. Because the PMC is required to program and boot the device, the CIPS IP must be present in every Versal adaptive SoC design.

In addition, the CIPS IP can only be accessed from the AMD Vivado™ IP integrator. Therefore, all Versal adaptive SoC designs include at least a portion of the design created using IP integrator, which contains the CIPS IP.

PS Wizard IP (AMD Versal™ AI Edge Series Gen 2 and AMD Versal™ Prime Series Gen 2)

Some devices use the Processing System (PS Wizard) IP instead of the CIPS IP. Similar to CIPS, the PS Wizard IP must be present in the Block Design (BD) for every Versal adaptive SoC device where it is available. The PS Wizard IP contains several key components for the Versal architecture, including the platform management controller (PMC), the processor subsystems (PS), and the Cache Coherent Interconnect for Accelerators (CCIX) PCIe® Module (CPM) on certain devices that contain it. The PMC manages programming and booting the Versal device, monitors the system, and protects the device from harmful attacks. Because the PMC is required to program and boot the device, the PS Wizard IP must be present in every Versal adaptive SoC design.

In addition, the PS Wizard IP can only be accessed from the AMD Vivado™ IP integrator. Therefore, all Versal adaptive SoC designs include at least a portion of the design created using IP integrator, which contains the PS Wizard IP.

Note: Unlike CIPS, the tool automatically inserts PS Wizard during the opt_design stage. This occurs if no instance of the PS Wizard IP is present on the BD in IP integrator based designs.

NoC IP

The NoC is a high-bandwidth, hardened interconnect that provides the backbone for all data movement in the Versal architecture. You interact with the NoC IP using standard AXI memory mapped or streaming interfaces. The NoC compiler aggregates the requested bandwidths and relative priorities for all traffic and allocates the physical routes appropriately.

The NoC is the only way to access the Versal adaptive SoC hardened memory controllers. In addition, NoC ports are available on the CIPS/PS Wizard, throughout the AI Engine array and the programmable logic (PL) fabric.

GT IP

In Versal devices, gigabit transceivers (GTs) are grouped into quads. This reduces overhead by enabling the GTs to share clocks and resets. The 2024.2 release introduces the Versal adaptive SoC Transceivers Wizard Subsystem. The advantages of this IP over the legacy Versal adaptive SoC Transceivers Wizard include:

1. You can instantiate multiple quads in the same IP.
2. Multiple GT quads can spread protocols.
3. You can instantiate IP directly in RTL and still support IP integrator designs.

All new designs must use the Versal adaptive SoC Transceivers Wizard Subsystem. Existing designs can continue to use the Versal adaptive SoC Transceivers Wizard, but the tool is phasing it out. To aid migration, the two wizards can coexist in the same design, but they cannot interact.

The IP integrator configured the Versal adaptive SoC Transceivers Wizard using parameter propagation. You can configure the new Versal adaptive SoC Transceivers Wizard Subsystem in four different ways:

1. Manually. Configure all settings on the IP itself.
2. By selecting preset configurations. This most closely resembles the configuration of the Versal adaptive SoC Transceivers Wizard as this represents the parent IP configurations.
3. Targeting a specific AMD IP from the Import Settings window. This method reproduces the parameter propagation from the IP integrator but can be used in both IP integrator and RTL designs.
4. Importing custom settings from a file. This method replaces the bridge IP for connecting custom RTL to the transceivers. A configuration file expresses the configuration of the transceivers connected to an IP.

Pin planning for Versal GTs remains with the Vivado Hard Block Planner and not part of the IP generation.