Design Planning Considerations for the Traditional Design Flow - Design Planning Considerations for the Traditional Design Flow - 2026.1 English - UG1387

When using the Versal adaptive SoC traditional design flow, you must consider the following when planning your design:

CIPS/PS Wizard IP

The Vivado tools generate the final programmable device image (PDI). Include CIPS IP in the design to properly generate the PDI. This is necessary even if the processing system is not used. The PMC resides in the CIPS and it boots the Versal device.

Design Hierarchy and NoC Compiler

In the Versal adaptive SoC design, you can instantiate one or more NoC IP. Place all NoC IP under a single BD hierarchy. When validating the topmost BD, the system automatically calls the NoC compiler. The compiler gains complete visibility of all NoC master and slave units in the design, including their connectivity, bandwidth requirements, and relative priorities.

Note: If the design uses a BD top, the NoC Compiler always has visibility into all the NoC IP cores instantiated in the design.

Simulation

Simulation requires special connections to be created to the NoC to correctly model its connectivity. When the design is exported for simulation, an additional level of hierarchy is added to the design to represent the NoC connectivity. This process is transparent to you and is required for the NoC to simulate correctly.

The following figures show examples of the traditional design flows.

Figure 1. Traditional Design Flow

Figure 2. Traditional Design Flow Using IP Integrator to Customize PS Wizard