Design Planning Considerations for Tandem Configuration - 2025.2 English - UG1387

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)

Document ID
UG1387
Release Date
2025-12-17
Version
2025.2 English

Tandem Configuration is a staged configuration that brings up the PCIe protocol less than 100 ms after power to Versal adaptive SoC is stable. This is achieved using a stage 1 programmable device image (PDI). The rest of the device, including the PL, can be downloaded by the user application as a stage 2 PDI. In Versal adaptive SoC, Tandem Configuration is accomplished using the CPM integrated block. Tandem Configuration supports the Tandem PCIe and Tandem PROM modes. For more information, see the Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347).

Unlike previous architectures, stage 1 configuration elements are hardened blocks in the CPM. The CPM portion of the CIPS/PS Wizard IP contains an option to enable Tandem Configuration (not all devices have CPM resources). You can select either Tandem PROM or Tandem PCIe. The programmable device image (PDI) is constructed with two partitions: stage 1 and stage 2. The stage 1 portion of the design includes configuration of the PMC and CPM, and the stage 2 portion of the design includes everything else.

If you select the Tandem PROM mode, the stage 1 and stage 2 portions are generated in a single PDI file and can be loaded automatically through a configuration flash interface. If you select the Tandem PCIe mode, the stage 1 PDI file is loaded through the configuration flash, and the stage 2 PDI is loaded through the PCIe link. Both Tandem PCIe and DFX over PCIe solutions require additional design connectivity and host interaction to configure the device.

When Segmented Configuration is enabled for devices with CPM5 resources, Tandem Configuration is automatically enabled. The boot PDI contains both stage 1 and the non-PL portion of stage 2, ensuring the CPM5 end point can link train within 100 ms. Then, the PLD PDI can be loaded over the PCIe link or any other available configuration interface.