Design Planning Considerations for Tandem Configuration - Design Planning Considerations for Tandem Configuration - 2026.1 English - UG1387

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)

Document ID
UG1387
Release Date
2026-07-22
Version
2026.1 English

Tandem Configuration is a staged configuration that brings up the PCIe protocol less than 100 ms after power to Versal adaptive SoC is stable. A stage 1 programmable device image (PDI) achieves this. The user application can download the rest of the device, including the PL, as a stage 2 PDI.

In Versal adaptive SoC, Tandem Configuration is accomplished using only hard IP (CPM4, CPM5, MDB5) integrated block. Tandem Configuration supports the Tandem PCIe and Tandem PROM modes. Tandem Configuration is not supported for PL PCIe endpoints in any Versal adaptive SoC. For more information, refer to the Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347).

Unlike previous architectures, the CPM contains hardened blocks for stage 1 configuration elements. The CPM portion of the CIPS/PS Wizard IP contains an option to enable Tandem Configuration (not all devices have CPM resources). You can select either Tandem PROM or Tandem PCIe. The programmable device image (PDI) includes two partitions: stage 1 and stage 2. The stage 1 portion of the design includes configuration of the PMC and CPM, and the stage 2 portion of the design includes everything else.

If you select the Tandem PROM mode, the stage 1 and stage 2 portions are generated in a single PDI file. A configuration flash interface can automatically load them. If you select the Tandem PCIe mode, the configuration flash loads the stage 1 PDI file. The PCIe link then loads the stage 2 PDI. Both Tandem PCIe and DFX over PCIe solutions require additional design connectivity and host interaction to configure the device.

When Segmented Configuration is enabled for devices with hard IP (CPM4, CPM5, MDB5) resources configured in endpoint mode, Tandem Configuration is automatically enabled. The boot PDI contains both stage 1 and the non-PL portion of stage 2, ensuring the endpoint can link train within 100 ms. Load the PLD PDI over the PCIe link or any other available configuration interface.