Design Planning Considerations for AI Engine and Programmable Logic Integration - Design Planning Considerations for AI Engine and Programmable Logic Integration - 2026.1 English - UG1387

You can develop Versal adaptive SoC designs by combining hardware development with Vivado tools and software development with Vitis tools. Various design methodologies are available for design development. Select a methodology based on the specific requirements of the design flow. These methodologies can significantly improve the efficiency of the design development flow.

AMD recommends developing the hardware design in Vivado. If a hardware platform is available, you can use it in Vitis to develop the software components. You can develop Versal adaptive SoC designs using either the Vitis Integrated flow or Vitis Export to Vivado flow.

AMD recommends using the Vitis Export to Vivado flow after completing AI Engine and HLS software component development. Continue hardware development exclusively in Vivado after exporting. This flow enables you to complete the hardware design development and verification in Vivado.

1. For the Vitis Export to Vivado flow, the steps for the flow are as follows:
   1. Create the hardware design using Vivado.
   2. Export the extensible xsa from Vivado.
   3. Compile kernels (AI Engine/HLS) in Vitis to generate libadf.a and .xo.
   4. Generate the .vma file by linking compiled outputs, extensible.xsa, and config files with switch --export_archive. v++ --link does not run synthesis and implementation.
   5. Import the .vma into Vivado.
   6. Perform the design modifications in Vivado.
   7. Run the synthesis and implementation.
   8. Generate the fixed.xsa using write_hw_platform -fixed.
   9. Generate the xclbin from fixed.xsa (Vivado generated) using the v++ --package.
   10. Take the design to hardware.

   For information on the Vitis Export to Vivado flow, refer to Packaging for Vitis Export to Vivado Flow in the Embedded Design Development Using Vitis (UG1701).

2. Use the Vitis Integrated flow on hardware design platforms built in Vivado. This flow enables you to use the platform and plug in AI Engine/HLS software components of the application. This flow is typically useful when the hardware development is complete and software components need to be added or modified. The steps for the flow are as follows:
   1. Create the hardware design using Vivado.
   2. Export the extensible xsa from Vivado.
   3. Compile kernels (AI Engine/HLS) in Vitis to generate libadf.a and .xo.
   4. Generate the fixed.xsa by linking compiled outputs, extensible.xsa, and config files. Synthesis and implementation runs in this stage. Fixed xsa is generated by Vitis after closing all design runs.
   5. Generate the xclbin from the fixed.xsa (Vitis generated) using the v++ --package.
   6. Take the design to hardware.

   For more information on report generation, refer to Controlling Report Generation in the Data Center Acceleration using Vitis (UG1700).

3. Use this flow for the Vitis Design Development without a platform. It targets devices for which AMD has not released evaluation boards or platforms. Using this flow, you can start the software development of AI Engine/HLS components of your application. This flow does not require the use of xsa (generated from Vivado) for your software development. The steps for the flow are as follows:
   1. Compile AI Engine with the --part.
   2. Generate the XSA using v++ --link --part ….
   3. Compile the HLS with generate XSA.
   4. Generate the fixed.xsa by linking compiled outputs, extensible.xsa, and config files. Synthesis and implementation runs in this stage. Fixed xsa is generated by Vitis after closing all design runs.
   5. Generate the xclbin from the fixed.xsa (Vitis generated) using the v++ --package.
   6. Take the design to hardware.

   For more information, refer to the Data Center Acceleration using Vitis (UG1700).