Design Creation with RTL - Design Creation with RTL - 2026.1 English

Design Creation with RTL - Design Creation with RTL - 2026.1 English - UG1387

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)

Document ID

UG1387

Release Date

2026-07-22

Version

2026.1 English

AMD requires the use of the AMD Vivado™ IP integrator to instantiate and configure the CIPS/PS Wizard and NoC IP for AMD Versal™ devices. The CIPS/PS Wizard IP contains the platform management controller (PMC). You must boot and configure all Versal devices. The CIPS/PS Wizard IP is only available in IP integrator.

Although not required, AMD recommends using the IP integrator to create the top-level RTL wrapper for your design. Enabling the Vivado tools to maintain the RTL wrapper simplifies the simulation of the design. The Vivado tools can automatically connect proper simulation models for the NoC IP.

You can configure the CIPS/PS Wizard and NoC in the IP integrator. Specify all external interfaces to the rest of the design. Instantiate the resulting block design in the top-level RTL. This approach limits the CIPS/PS Wizard and NoC to a subset of the larger system. However, you must manually ensure the proper simulation models connect correctly in their RTL wrappers.

Note: Refer to the Vivado Design Suite User Guide: I/O and Clock Planning (UG899) for more information on the I/O planning process. This guide also covers performing port assignments with a PCB designer in pre-RTL design and using clock resources.