The following figure shows the four major steps that define good constraints. The steps follow the timing constraints precedence and dependency rules. They also follow the logical way of providing information to the timing engine to perform the analysis.
- The first two steps cover the timing assertions, in which clock waveforms and I/O delay constraints derive the default timing path requirements.
- During the third step, relationships between the asynchronous/exclusive clock domains that share at least one logical path are reviewed. You enter clock groups or false path constraints to ignore the timing analysis on these paths, based on the nature of the relationships.
- The last step corresponds to the timing exceptions. The designer can alter the default timing path requirements. They can ignore, relax, or tighten them using specific constraints.
The timing engine generates various reports that enable the tasks of constraints identification, constraints creation, and constraints validation. The timing engine only works with a fully mapped netlist, for example, after synthesis. Create the first set of constraints with the post-synthesis netlist. This approach allows for interactive analysis and reporting on the constraints, although you can enter constrains with an elaborated netlist.
AMD recommends using the Timing Constraints Wizard when creating timing constraints for a new design or completing existing constraints. The Timing Constraints Wizard helps quickly identify missing constraints for the first three steps in the previous figure. The Timing Constraints Wizard follows the methodology described in this section to ensure the design constraints are safe and reliable for proper timing closure. You can find more information on the Timing Constraints Wizard in Vivado Design Suite User Guide: Using Constraints (UG903).
The following sections describe in detail the four steps described above:
- Defining Clock Constraints
- Constraining Input and Output Ports
- Defining Clock Groups and CDC Constraints
- Specifying Timing Exceptions
Refer to each section for a detailed methodology and use case when you are at the appropriate step in the constraint creation process.