Output delays are similar to input delays. However, they refer to the output path minimum and maximum time outside the device. This ensures functionality under all conditions.
The output delay values for both types of analysis are:
Output Delay(max) = Tsetup + Ddata(max) + Dclock_to_FPGA(max) - Dclock_to_ExtDev(min)
Output Delay(min) = Ddata(min) - Thold + Dclock_to_FPGA(min) - Dclock_to_ExtDev(max)The following figure shows a simple example of output delay constraints for both
setup (max) and hold (min) analysis, assuming the sysClk
clock has already been defined on the CLK port:
set_output_delay -max -clock sysClk 2.4 [get_ports DOUT]
set_output_delay -min -clock sysClk -1.1 [get_ports DOUT]
The output delay corresponds to the delay on the board before the capture edge. A regular system synchronous interface has balanced clock and data traces on the board. The setup time of the destination device defines the output delay value for max analysis. The destination device hold time defines the output delay for min analysis.
The specified min output delay indicates the minimum delay the signal incurs after exiting the design. This delay occurs before the signal is used for hold analysis at the destination device interface. Thus, the delay inside the block can be that much smaller.
A positive value for min output delay means that the signal can
have negative delay inside the design. This is why min output delay is often
negative. The following code example shows a delay inside the design. The
delay for DOUT must be at least +0.5 ns to meet the hold
time requirement.
set_output_delay -min -0.5 -clock CLK [get_ports DOUT]