Defining Interfaces - Defining Interfaces - 2026.1 English - UG1387

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)

Document ID
UG1387
Release Date
2026-07-22
Version
2026.1 English

The primary difference between the Vivado IP flow and the Vitis kernel flow in Vitis HLS is the handling of the design interfaces. In the Vivado IP flow, the designer must explicitly manage interfaces. In the Vitis kernel flow, Vitis HLS automatically infers the following AXI interfaces:

  • AXI4 memory-mapped
  • AXI4-Lite
  • AXI4-Stream

Before starting a project with either flow, you need to understand how Vitis HLS handles interfaces. Refer to this link in the Vitis High-Level Synthesis User Guide (UG1399).