Defining Input Delays - Defining Input Delays - 2026.1 English - UG1387

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)
Document ID
UG1387
Release Date
2026-07-22
Version
2026.1 English

The clock at the device interface defines the input delay. Unless set_clock_latency is specified on the source pin of the reference clock, the input delay corresponds to the absolute time from the launch edge, through the clock trace, the external device and the data trace. If you already specified clock latency separately, you can ignore the clock trace delay.

Figure 1. Input Delay Computation

The input delay values for both types of analysis are:

Input Delay(max) = Tco(max) + Ddata(max) + Dclock_to_ExtDev(max) - Dclock_to_FPGA(min)
Input Delay(min) = Tco(min) + Ddata(min) + Dclock_to_ExtDev(min) - Dclock_to_FPGA(max)

The following figure shows a simple example of input delay constraints for both setup (max) and hold (min) analysis. Assume the sysClk clock has already been defined on the CLK port:

set_input_delay -max -clock sysClk 5.4 [get_ports DIN]
set_input_delay -min -clock sysClk 2.1 [get_ports DIN]
Figure 2. Interpreting Min and Max Input Delays

A negative input delay means that the data arrives at the interface of the device before the launch clock edge.